Transistor channel

ABSTRACT

A transistor device includes a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion, a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer, and a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer. The second conductivity type is different than the second conductivity type, and the second semiconductor material is different from the first semiconductor material.

PRIORITY INFORMATION

This application is a continuation-in-part of U.S. patent application Ser. No. 13/871,465 filed Apr. 26, 2013, and entitled “A Semiconductor Device and Fabricating the Same,” which claims the benefit of Provisional Application No. 61/778,693, the disclosures of which are hereby incorporated by reference in their entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth in the past several decades. Technological advances in semiconductor materials and design have produced increasingly smaller and more complex circuits. These material and design advances have been made possible as the technologies related to processing and manufacturing have also undergone technical advances. As a size of the smallest component has decreased, numerous challenges have risen. For example, a three dimensional transistor, such as a fin-like field-effect transistor (FinFET), has been introduced. Although existing devices and methods of fabricating devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, a limitation of an effective gate length raises challenges in semiconductor device development, including with FinFETs. It is desired to have improvements in this area.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flow chart showing an illustrative method for fabricating a semiconductor device, according to one example of principles described herein.

FIGS. 2-6 illustrate cross sectional views of an illustrative semiconductor device at fabrication stages described in the method of FIG. 1, according to one example of principles described herein.

FIGS. 7A-7H are diagrams showing an illustrative process for forming embedded channels for transistor devices, according to one example of principles described herein.

FIG. 8 is a diagram showing an illustrative tip with a higher dopant concentration, according to one example of principles described herein.

FIG. 9 is a diagram showing an illustrative tip with a superlattice structure, according to one example of principles described herein.

FIG. 10 is a flowchart showing an illustrative method for forming a transistor with an improved channel, according to one example of principles described herein.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Examples of semiconductor devices that can benefit from one or more embodiments of the present application are semiconductor devices. The semiconductor device, for example, may be a complementary metal-oxide-semiconductor (CMOS) device comprising a P-type metal-oxide-semiconductor (PMOS) device and an N-type metal-oxide-semiconductor (NMOS) device. The following disclosure will continue with a semiconductor device example to illustrate various embodiments of the present application. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed.

FIG. 1 is a flowchart of one example of a method 100 of fabricating one or more semiconductor devices according to aspects of the present disclosure. The method 100 is discussed in detail below, with reference to a semiconductor device 200 shown in FIGS. 2 to 6 for the sake of example.

Referring to FIGS. 1 and 2, the method 100 begins at step 102 by providing a substrate 210. The substrate 210 may be a bulk silicon substrate. Alternatively, the substrate 210 may comprise an elementary semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or combinations thereof. Possible substrates 210 also include a silicon-on-insulator (SOI) substrate. SOI substrates are fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.

The substrate 210 may include various doped regions depending on design requirements as known in the art. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; or combinations thereof. The doped regions may be formed directly on the substrate 210, in a P-well structure, in an N-well structure, in a dual-well structure, or using a raised structure. The substrate 210 may further include various active regions, such as regions configured for an N-type metal-oxide-semiconductor transistor device and regions configured for a P-type metal-oxide-semiconductor transistor device.

For a FinFET, the substrate 210 may include a plurality of fins formed by any suitable process including various deposition, photolithography, and/or etching processes. For example, fins are formed by patterning and etching the substrate 210.

The substrate 210 may include isolation regions 212 to isolate active regions of the substrate 210. The isolation region 212 may be formed using traditional isolation technology, such as shallow trench isolation (STI), to define and electrically isolate the various regions. The isolation region 212 comprises silicon oxide, silicon nitride, silicon oxynitride, an air gap, other suitable materials, or combinations thereof. The isolation region 212 is formed by any suitable process. As one example, the formation of an STI includes a photolithography process, an etch process to etch a trench in the substrate (for example, by using a dry etching and/or wet etching), and a deposition to fill in the trenches (for example, by using a chemical vapor deposition process) with one or more dielectric materials. The trenches may be partially filled, as in the present embodiment, where the substrate remaining between trenches forms a fin structure. In some examples, the filled trench may have a multi-layer structure such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

Referring again to FIGS. 1 and 2, the method 100 proceeds to step 104 by forming a first gate stack 220 over the substrate 210, including over (wrapping) a portion of fins in a FinFET, and a gate spacer 225 along sidewalls of the first gate stack 220. The first gate stack 220 may include a dielectric layer and a gate electrode layer. The first gate stack 220 can be formed by a procedure including deposition, photolithography patterning, and etching processes. The deposition processes may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. The photolithography patterning processes may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, and/or combinations thereof. The etching processes include dry etching, wet etching, and/or other etching methods.

In present embodiment, the first gate stack 220 is a dummy gate stack and is replaced later by a second gate stack. The dummy gate stack 220 may include the dielectric layer and the polysilicon layer.

The gate spacers 225 include a dielectric material such as silicon oxide. Alternatively, the gate spacers 225 may include silicon nitride, silicon carbide, silicon oxynitride, or combinations thereof. The gate spacers 225 may be formed by depositing a dielectric material over the first gate stack 220 and then anisotropically etching back the dielectric material.

Referring to FIGS. 1 and 3, the method 100 proceeds to step 106 by removing portions of the substrate 210, including portions of fins, at either side of the first gate stack 220 to form recesses 230A and 230B (collectively referred to as recesses 230). In the depicted embodiment, the recesses 230 are formed in a source region and a drain region of the field effect transistor 205, such that the first gate stack 220 interposes the recesses 230. They are referred to as the source recess 230A and the drain recess 230B. The recessing process may include dry etching process, wet etching process, and/or combination thereof. The recessing process may also include a selective wet etch or a selective dry etch. A wet etching solution includes a tetramethylammonium hydroxide (TMAH), a HF/HNO₃/CH₃COOH solution, or other suitable solution. The dry etching process may implement fluorine-containing gas (e.g., CF₄, SF₆, CH₂F₂, CHF₃, and/or C2F6), chlorine-containing gas (e.g., Cl₂, CHCl₃, CCl₄, and/or BCl₃), bromine-containing gas (e.g., HBr and/or CHBR₃), iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. The etching process may include a multiple-step etching to gain etch selectivity, flexibility and desired etch profile.

The etching process is controlled to achieve a desired profile of the recesses 230A and 230B. In the present embodiment, a profile of the recess 230A and 230B is formed to have at least one vertex 232A and 232B, respectively, of facets directed towards the first gate stack 220, as illustrated in FIG. 3. As an example, the vertex 232A is formed by two Si facets having (111) crystallographic orientation. A first distance d1 is defined as the distance between two nearest source and drain vertexes, 232A and 232B. In the present embodiment, the gate 220 with sidewall spacers 225 has a width greater than 30 nm, and the first distance d1 is equal or less than 40 nm. Although shown as points in the figures, in some embodiments, the source and drain vertexes, 232A and 232B can be rounded, and have a width that is equal to or less than 10 nm. As an example, the rounded vertex can be achieved by post recess-etch thermal anneal (the process temperature and pressure are >700 C and <100 torr, respectively.).

Referring to FIGS. 1 and 4, the method 100 proceeds to step 108 by forming epitaxial structures 240A and 240B (collectively referred to as epitaxial structures 240) in recesses 230A and 230B, respectively. In the present embodiment, the epitaxial structures 240 include a source/drain structure. The source/drain epitaxial structures 240 are formed by epitaxially growing a semiconductor material 242 in recesses 230. As a result, at least a portion of the source/drain epitaxial structure 240 has the same profile as the recesses 230.

The semiconductor material 242 includes single element semiconductor material such as germanium (Ge) or silicon (Si); or compound semiconductor materials, such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs); or semiconductor alloy, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP). In one embodiment the semiconductor material 242 is different than the material of the substrate 210. The source/drain epitaxial structures 240 have a suitable crystallographic orientation (e.g., a (100), (110), (111) or (311) crystallographic orientation). In an example, where an NFET device is desired, the source/drain epitaxial structures 240 may include an epitaxially growing silicon (epi Si, or Si:C) 242. In another example where a PPFET device is desired, source/drain epitaxial structures 240 may include an epitaxially growing silicon germanium (SiGe) 242. Si:C and SiGe can provide tensile and compressive strains to channel through S/D vertexs. The source/drain epitaxial structures 240 may be formed by one or more epitaxy or epitaxial (epi) processes. The epitaxial processes may include CVD deposition techniques (e.g., selective epitaxy growth (SEG), vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes.

The source/drain epitaxial structures 240 may be in-situ doped or undoped during the epi process. For example, the epitaxially grown SiGe source/drain features 240 may be doped with boron; and the epitaxially grown Si epi source/drain features may be doped with carbon, phosphorous, or both. If the source/drain epitaxial structures 240 are not in-situ doped, a second implantation process (e.g., a junction implant process) is performed to dope the source/drain epitaxial structures 240. One or more annealing processes may be performed to activate source/drain dopants in the epitaxial structures. The annealing processes may include rapid thermal annealing (RTA) and/or laser annealing processes.

Referring to FIGS. 1 and 5A, the method 100 proceeds to step 110 by removing the first gate stack 220 and further etching the substrate 210, including fins, to form a gate trench 250. The etching processes may include selective wet etch or selective dry etch, such that having an adequate etch selectivity with respect to the gate spacer 225. The etching process may be similar in many respects to those discussed above in association with FIG. 3. In the present embodiment, the gate trench 250 is formed with a profile having at least one gate vertex 255. In one embodiment, the gate vertex 255 is formed at a bottom of the gate trench 250 by two (111) facets of the Si substrate 210. In the present embodiment, a second perpendicular distance d2 between the gate vertex 255 and a horizontal line A-A connecting the source and drain vertexes, 232A and 232B is equal to or less than 30 nm. Although shown as a point in the figures, in some embodiments, the gate vertex 255 can be rounded, and have a width that is equal to or less than 10 nm. As an example, the rounded vertex can be achieve by post recess-etch thermal anneal (temperature>700 C at lower pressure (<100 torr)).

In another embodiment, after forming the gate trench 250, an ion-implantation is performed to dope a targeted region 256 in the substrate 210, located between the gate vertex 255, the source vertex 232A and drain vertex 232B, as shown in FIG. 5B.

Referring to FIGS. 1 and 6, the method 100 proceeds to step 112 by forming a second gate stack 260 in the gate trench 250. The second gate stack 260 may include a dielectric layer 262 and a gate electrode layer 264. It is understood that the gate stack may include additional layers such as interfacial layers, capping layers, diffusion/barrier layers, dielectric layers, conductive layers, other suitable layers, and/or combinations thereof. For example, the dielectric 262 may include an interfacial layer (IL) and a gate dielectric layer. An exemplary IL includes silicon oxide (e.g., thermal oxide or chemical oxide) and/or silicon oxynitride (SiON). The gate dielectric layer may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material includes HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO₂—Al2O₃) alloy, other suitable high-k dielectric materials, and/or combinations thereof.

The gate electrode layer 264 includes any suitable material, such as polysilicon, aluminum, copper, titanium, tantulum, tungsten, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof.

The gate dielectric layer 262 and gate electrode layer 264 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable methods, and/or combinations thereof.

A dielectric layer 270 is deposited over the substrate 210, including over the source/drain epitaxial structures 240 and the second gate stack 250. The dielectric layer 270 includes silicon oxide, silicon nitride, silicon carbide, oxynitride or other suitable materials. The dielectric layer 270 is deposited by a suitable technique, such as CVD, ALD, PVD, thermal oxidation, or combinations thereof. Additionally, a CMP process is performed to planarize the top surface of the second gate stack 260 and the dielectric layer 270.

Additional steps can be provided before, during, and after the method 100, and some of the steps described can be replaced, eliminated, or moved around for additional embodiments of the method 100. The IC device 200 may include additional features, which may be formed by subsequent processing. For example, various contacts/vias/lines and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) may be formed over the substrate, configured to connect the various features or structures of the IC devices 200. For example, a multilayer interconnection includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may implement various conductive materials including copper, tungsten, and/or silicide.

Based on the above, the present disclosure presents a semiconductor device and fabrication. The semiconductor device employs vertex structures for each of gate stack, source and drain structures. Vertexes of the gate, source and drain are formed to be separated with a quite small distance to each other. The semiconductor device also has an option of having a doped region located between vertexes of the gate stack, the source and the drain. Thus semiconductor device can work as a tunneling device, or a single electron transistor (SET), and demonstrates advances of small gate length, low Vt, low power consumption.

FIGS. 7A-7H are diagrams showing an illustrative process for forming embedded channels for transistor devices. FIG. 7A illustrates a first wafer 700 that includes a semiconductor substrate 702 having a first semiconductor material layer 704 formed thereon. The semiconductor substrate 702 may be, for example, a silicon-on insulator (SOI) substrate. Such a substrate may include a semiconductor layer, an insulator layer such as an oxide layer, and another semiconductor layer.

The first semiconductor material 704 is a semiconductor material that may be designed for an NMOS transistor. Thus, the semiconductor type may have an N-type conductivity. The first semiconductor material 704 is chosen such that the channel region is able to be properly strained in order to enhance the corresponding mobility, such as tensile strain in the channel region of the NMOS transistor in the present example. The first semiconductor material 704 may be made of silicon germanium (SiGe) in one example. The first semiconductor material 704 may be epitaxially grown on the semiconductor substrate 702. In one example, the first semiconductor material 704 may be formed using a low pressure chemical vapor deposition (LPCVD) process. Such process may take place at a temperature within a range of about 800-1100 degrees Celsius. The process may take place at a pressure within a range of about 1-600 torr.

FIG. 7B is a diagram showing a second wafer 701 that is to eventually be bonded to the first wafer 700. The second wafer 701 includes a sacrificial substrate 706 and a second semiconductor material layer 708. The sacrificial substrate 706 is referred to as such because, as will be described below, it will eventually be removed. The sacrificial substrate 706 may be made of, for example, indium phosphorous (InP).

The second semiconductor material 708 may be designed for a PMOS transistor device. Thus, the second semiconductor material may have a P-type conductivity. The second semiconductor material 708 is chosen such that a channel region formed therein is able to be properly strained in order to enhance the corresponding mobility, such as compressive strains in the channel region of the PMOS transistor in the present example. The second semiconductor material 708 may be made of, for example, indium gallium arsenide (InGaAs). The second semiconductor material layer 708 may be formed through an epitaxial process. The second semiconductor material layer 708 may be formed using a metal-organic chemical vapor deposition (MOCVD) process. Such a process may occur at temperature within a range of about 500-700 degrees Celsius. Such a process may occur at a pressure of about 75 torr.

FIG. 7C is a diagram showing a combined wafer 703 after a bonding of the first wafer 700 and the second wafer 701. The bonding is performed such that the second semiconductor material 708 is bonded to the first semiconductor material 704 with a bonding layer 710. Before the bonding occurs, a surface passivation process can be applied to the second semiconductor material layer 708, depending on the type of material used for the second semiconductor material layer 708. Additionally, a plasma post oxidation process can be performed on the first channel layer material 704, depending on the type of material used for the first semiconductor material layer 704. The bonding layer 710, which is applied before the bonding process occurs, may be made of aluminum oxide (Al₂O₃). The bonding layer 710 may be applied to either wafer 700, 701 through atomic layer deposition (ALD).

FIG. 7D is a diagram showing removal of the sacrificial substrate 706. The sacrificial substrate 706 is removed after the bonding process is complete. The sacrificial substrate 706 can be removed using a wet etch process. For example, a hydrochloric acid may be used to remove the sacrificial substrate 706.

FIG. 7E is a diagram showing patterning of the combined wafer 703 to form a first structure in a first region 705 and a second structure in a second region 707. Through subsequent processes, the first structure in the first region 705 will become a first transistor device and the second structure in the second region 707 will become a second transistor device. Particularly, the first structure will become an NMOS device and the second structure will become a PMOS device. The combined wafer 703 may be patterned using various photolithographic techniques. For example, a photoresist may be used to form the desired pattern. Then, an anisotropic etching process, such as a dry etching process can be used to remove portions of the combined wafer that are exposed according to the pattern. The etching gas used for such an etching process may be a mix of chlorine and nitrogen or a mix of chlorine and argon. The bias power used for the etching process may be below 25 watts.

FIG. 7F is a diagram showing removal of the second semiconductor material 708 and the bonding layer 710 from the first structure in the first region 705. Thus, the first semiconductor material layer 704 in the first region 705 is exposed. Removal of the second semiconductor material 708 may involve various photolithographic techniques. For example, photoresist can be used to cover the second region 707 and other features of the wafer that are not intended to have the second semiconductor material layer 708 removed. Then, a wet etching process can be used to remove the exposed portions of the second semiconductor material layer 708. The wet etching process may include one of a variety of wet etching solutions such as HCl or H₃PO₄.

FIG. 7G is a diagram showing formation of gate structures 712, 716. Particularly, a first gate 712 is formed in the first region 705 and a second gate 716 is formed in the second region 707. The gate structures 712, 716 may be formed by various fabrication techniques. In one example, the gate structures 712, 716 may be formed in a manner similar to the gate device described above with respect to FIGS. 2-6. Particularly, in some examples, the gate structures 712, 716 may include a gate vertex as described above.

FIG. 7H is a diagram showing formation of source/drain regions 714, 718. Particularly, source/drain regions 714 are formed within the first semiconductor material layer 704 in the first region 705 and source/drain regions 718 are formed in the second semiconductor material layer 708 in the second region 707. The source/drain regions 714, 718 are formed by first removing portions of the underlying semiconductor material and then deposition the source/drain material within the removed portion.

Source/drain regions 714 can be formed by removing portions of the first semiconductor material layer 704 to form recesses on both sides of the gate 712. Material may be removed by using an anisotropic etching process such as a dry etching process in addition to a wet etching process such as TMAH wet etching, or a combination of both. The removal process may be a multi-step process to obtain the desired profile. After the removal process, there will be recesses formed in a shape such that a tip will face towards the channel region underneath the gate 712. Those recesses may then be filled with the source/drain material. The source/drain material may be silicon germanium doped with a dopant for a PMOS device such as Boron. The source/drain regions 714 may be formed through an LPCVD process that utilizes a silicon germanium based precursor gas as well as a gas containing the desired type of dopant such as B₂H₆. The LPCVD process may take place at a temperature within a range of about 300-800 degrees Celsius and at a pressure within a range of about 1-500 torr.

Source/drain regions 718 can be formed by removing portions of the second semiconductor material layer 708 to form recesses on both sides of the gate 716. Material may be removed by using multistep wet etching processes that use various wet etchants such as H₃PO₄, H₂O₂, and HCl or a mixture thereof. Dry etching processes may be used as well. After the removal process, there will be recesses formed in a shape such that a tip will face towards the channel region underneath the gate 716. Those recesses may then be filled with the source drain material. The source/drain material may be silicon germanium doped with a dopant for a NMOS device such as phosphorous. The source/drain regions 718 may be formed through an LPCVD process that utilizes a silicon germanium based precursor gas as well as a gas containing the desired type of dopant such as PH3 or AsH3. The LPCVD process may take place at a temperature within a range of about 300-800 degrees Celsius and at a pressure within a range of about 1-500 torr.

FIG. 7H illustrates a structure in which an NMOS device 705 and a PMOS device 707 are formed adjacent to each other. The PMOS device 707 is on a different level than the NMOS device 705. Specifically, the PMOS device 707 is on a higher level than the NMOS device 705 with respect to the substrate 702. It is understood that the features of FIG. 7H do not necessarily include all features that may be part of a transistor within an integrated circuit. For example, additional dielectric layers, metal contacts, and other features are part of the transistor device.

Use of principles described herein provides a number of advantages. For example, using specific types of channel materials for NMOS and PMOS devices can provide more efficient transistors. Specifically, the specific types of materials can lower the tunneling barrier and thus the voltage threshold. An integrated circuit made of such transistors can consume less power during operation.

For example, for an NMOS transistor, using a silicon germanium channel and source drain regions made of doped silicon germanium, there is less lattice mismatch between the channel and the source/drain regions. This leads to fewer dislocations within the source/drain regions. Similarly, for a PMOS transistor, using indium gallium arsenide as a channel material and using doped silicon germanium for the source/drain regions, there is also less lattice mismatch.

FIG. 8 is a diagram 800 showing an illustrative tip 804 with a higher dopant concentration than the remaining portion 802 of the source/drain region. As described above, the source/drain regions having a vertex pointing towards the channel. For example, in the case of a PMOS device having source/drain regions doped with boron, there is a higher concentration of boron at the tip 804 of the device. The tips 804 with a higher dopant concentration may be formed before the remaining portion 802 of the source/drain region is formed. Specifically, after a portion of the semiconductor material is removed and before the source/drain material is deposited within the recess, the higher concentrated tips 804 can be formed within the recess at the appropriate location. In one example, the thickness 806 of the higher dopant concentrated tips 804 is about 5 nanometers.

FIG. 9 is a diagram 900 showing an illustrative tip 904 with a superlattice structure. The remaining portions 902 of the source/drain region may be the normal source/drain material. A superlattice structure alternates between two types of semiconductor material. Specifically, the superlattice structure alternates between a first type of material 906 and a second type of material 908. For example, in the case of a PMOS device, the first material 906 may be silicon germanium doped with boron and the second material 908 may be silicon doped with boron. In the case of a NMOS device, the first material 906 may be silicon germanium without dopant and the second material 908 may be silicon doped with phosphorous. In some cases, the two different materials 906, 908 may both be doped silicon germanium but with two different concentrations of germanium. The thickness 910, 912 of each section of material may be about 3 nanometers.

Using the techniques above with respect to the tips of the source/drain regions, current can be more efficiently directed through the channel. This allows the tunneling voltage to be further reduced, thus allowing the transistor to operate on less power.

FIG. 10 is a flowchart showing an illustrative method for forming a transistor with an improved channel. According to the present example, the method 1000 may be used to form the structure illustrated in FIG. 7H. The method 1000 includes a step 1002 for providing a first wafer comprising a semiconductor layer and a first semiconductor material layer. The semiconductor layer may be a silicon-on-insulator substrate. The first semiconductor material layer may be a material intended for use in an NMOS device.

The method 1000 further includes a step 1004 for bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer. The second channel layer may be a material intended for use in a PMOS device. The method further includes a step 1006 for removing the sacrificial layer. This is done after the wafers have been bonded.

The method 1000 further includes a step 1008 for patterning the bonded substrates to create a first structure in a first region and a second structure in a second region. The first structure is used to form the NMOS device and the second structure is used to form the PMOS device. The method 1000 further includes a step 1010 for removing the second semiconductor material from the first feature. This exposes the first semiconductor material.

The method 1000 further includes a step 1012 for forming a first type of transistor in the first semiconductor material in the first region. This involves forming a gate device and source/drain regions adjacent to the gate device. The source/drain regions may be formed such that they have vertexes that point towards the channel region underneath the gate. The transistor device may have features as described in FIGS. 2-9.

The method 1000 further includes a step 1014 for forming a second type of transistor in the second semiconductor material in the second region. This involves forming a gate device and source/drain regions adjacent to the gate device. The source/drain regions may be formed such that they have vertexes that point towards the channel region underneath the gate.

According to one example, a transistor device includes a substrate having a first region and a second region, a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion. The device further includes a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer, and a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer. The second conductivity type is different than the second conductivity type, and the second semiconductor material is different from the first semiconductor material.

According to one example, a transistor device includes a gate device, a source region having a vertex pointing towards a channel beneath the gate device, and a drain region having a vertex pointing towards the channel. A tip at the vertex of the source region and a tip at the vertex of the drain region comprise a superlattice structure.

According to one example, a method for fabricating a semiconductor device includes providing a first wafer comprising a substrate and a first semiconductor material layer, bonding the first wafer to a second wafer, the second wafer comprising a sacrificial layer and a second semiconductor material layer, removing the sacrificial layer, patterning the bonded wafers to create a first structure and a second structure, removing the second semiconductor material from the first structure, forming a first type of transistor in the first semiconductor material of the first structure, and forming a second type of transistor in the second semiconductor material of the second structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A transistor device comprising: a substrate having a first region and a second region; a first semiconductor layer of a first semiconductor material having a first portion over the first region and a second portion over the second region, the first portion being separated from the second portion wherein the first portion and second portion each extend respectively from a first bottom surface to a first top surface; a second semiconductor layer of a second semiconductor material over the second portion of the first semiconductor layer, wherein the second semiconductor layer extends from a second bottom surface to a second top surface, the second bottom surface of the second semiconductor layer being disposed above the first top surface of the first portion of the first semiconductor layer; a first transistor of a first conductivity type, the first transistor disposed within the first region and having a first set of source/drain regions formed in the first semiconductor layer and a first gate structure, wherein the first set of source/drain regions each comprise planar edges that extend to vertexes pointing towards a channel within the first transistor and include a main portion and a tip portion adjacent the vertexes, and wherein the tip portion comprises a superlattice structure and the main portion includes a non-superlattice structure, the superlattice structure alternating between individual layers of silicon germanium and silicon, both the silicon germanium and silicon having a same type of dopant and extending vertically in the tip portion from planar edge to planar edge; and a second transistor of a second conductivity type, the second transistor disposed within the second region and having a second set of source/drain regions formed in the second semiconductor layer and a second gate structure; wherein the second conductivity type is different than the first conductivity type, and the second semiconductor material is different from the first semiconductor material; and wherein the first gate structure is at a first level above the substrate and the second gate structure is at a second level above the substrate, the second level greater than the first level and the first and second levels defined by a bottommost surface of the first and second gate structure respectively.
 2. The device of claim 1, wherein the first semiconductor material comprises silicon germanium (SiGe) and the second semiconductor material comprises indium gallium arsenide (InGaAs).
 3. The device of claim 1, further comprising, a bonding layer between the first semiconductor layer and the second semiconductor layer over the second region, wherein the bonding layer is disposed over the first top surface of the second portion of the first semiconductor material, and wherein the bonding layer is disposed at a greater height from an underlying substrate than the first top surface of the first portion of the first semiconductor layer.
 4. The device of claim 3, wherein the bonding layer comprises an oxide material.
 5. The device of claim 1, wherein the first set of source/drain regions and the second set of source drain regions are epitaxially grown.
 6. The device of claim 1, wherein the first set of source/drain regions have the same type of dopant of boron.
 7. The device of claim 1, wherein the second set of source/drain regions comprise silicon germanium doped with phosphorous.
 8. The device of claim 1, wherein the second set of source/drain regions comprise planar edges that extend to vertexes pointing towards a channel within respective transistors.
 9. The device of claim 8, wherein each of the first set of source/drain regions and the second set of source/drain regions each include a main portion and a tips of the vertexes portion, wherein the tips of the vertexes portion of the second set of source/drain regions are doped with a higher concentration of a second dopant than the main portions; and wherein the tips of the vertexes portion of the first set of source/drain regions are doped with a higher concentration of the same type of dopant.
 10. The device of claim 8, wherein the second set of source/drain regions each include a main portion and a tip of the vertex portion, and wherein the tip of the vertex portions of the second set of source/drain regions each comprise a superlattice structure and the main portions of the second set of source/drain regions have a non-superlattice structure.
 11. The device of claim 10, wherein the superlattice structure of the second set of source/drain regions alternates between individual layers of silicon germanium and silicon, both the silicon germanium and silicon having a same type of second dopant and extending vertically in the tips of each of the second set of source/drain regions from planar edge to planar edge.
 12. The device of claim 10, wherein sections of the superlattice structure have a thickness of about 3 nanometers.
 13. A transistor device comprising: a gate stack on a substrate; a source region disposed in a first recess having two planar surfaces defined by a facet of the substrate having a first crystallographic orientation and angled inwards with respect to the gate stack towards a first vertex pointing towards a channel beneath the gate device; and a drain region disposed in a second recess having two planar surfaces defined by a facet of the substrate having the first crystallographic orientation and angled inwards with respect to the gate stack towards a second vertex pointing towards the channel; wherein a tip at the first vertex of the source region comprises a first superlattice structure having a plurality of individual layers that extend up to two planar surfaces of the first recess and the first vertex and a tip at the second vertex of the drain region comprises a second superlattice structure having a plurality of individual layers that extend up to the two planar surfaces of the second recess and the second vertex, wherein the source region and the drain region adjacent the tip of the respective first vertex and second vertex are non-superlattice structure.
 14. The device of claim 13, wherein the plurality of individual layers of each of the first and second superlattice structures alternate between silicon germanium and silicon in a direction that is substantially perpendicular to the substrate, both the silicon germanium and silicon having a same type of dopant.
 15. The device of claim 13, wherein each of the plurality of the individual layers of the first superlattice structure have a thickness of about 3 nanometers.
 16. A semiconductor device comprising: a first transistor, the first transistor comprising: a first gate stack disposed over a substrate and on a top surface of a first semiconductor layer; a first source epitaxial structure doped with a first dopant of boron and filling a first recess in the first semiconductor layer, the first recess having two planar surfaces defined by a facet of the substrate and extending in to a vertex pointing towards a channel beneath the first gate stack, wherein a tip of the vertex of the first source epitaxial structure has a higher concentration of the first dopant than any other portion of the first source epitaxial structure; and a first drain epitaxial structure doped with the first dopant and filling a second recess in the first semiconductor layer, the second recess having two planar surfaces defined by a facet of the substrate and extending in to a vertex pointing towards the channel, wherein a tip of the vertex of the first drain epitaxial structure has a higher concentration of the first dopant than any other portion of the first drain epitaxial structure, wherein the tip of the vertex of the first source epitaxial structure is spaced apart from the tip of the vertex of the first drain epitaxial structure by a first distance; and a second transistor, the second transistor comprising a second gate stack over the substrate and on a top surface of a second semiconductor layer, a portion of the first semiconductor layer underlying the second semiconductor layer; a second source epitaxial structure doped with a second dopant and filling a third recess in the second semiconductor layer; a second drain epitaxial structure doped with the second dopant and filling a fourth recess in the second semiconductor layer, wherein a bottom surface of the second semiconductor layer is spaced a greater height from a top surface of the substrate than the top surface of the first semiconductor layer under the first gate stack.
 17. The device of claim 16, wherein one of the tip of the vertex of the first source epitaxial structure and the tip of the vertex of the first drain epitaxial structure comprises a superlattice structure that is constrained within the first source epitaxial structure or the first drain epitaxial structure, wherein a portion of the vertex adjacent the superlattice structure has a non-superlattice structure.
 18. The device of claim 16, where the first gate stack has a two parallel sides extending above the substrate that intersect two planar surfaces that are defined by a facet on a first crystallographic orientation of the substrate towards a vertex pointing towards the channel, wherein a tip of the vertex of the first gate stack is spaced apart from the tip of the vertex of the first source epitaxial structure by a second distance, wherein the tip of the vertex of the first gate stack is away from the tip of the vertex of the first drain epitaxial structure by the second distance.
 19. The device of claim 16, wherein the tip of the vertex of the first source epitaxial structure and the vertex of the first drain epitaxial structure of the first transistor include superlattice structures that alternate between individual layers of silicon germanium and silicon, wherein the individual layers each extend vertically between the two planar surfaces. 